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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD9802 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1997 ccd signal processor for electronic cameras functional block diagram shp AD9802 pgacont1 pgacont2 clamp clpdm pblk pin din shd adcclk timing generator cmlevel vrt vrb stby reference s/h clpob clamp dout 10 pga cds a/d adcin adcmode mux drvdd dvdd advdd acvdd features 10-bit, 18 msps a/d converter 18 msps full speed correlated double sampler (cds) low noise, wideband pga internal voltage reference no missing codes guaranteed +3 v single supply operation low power cmos: 185 mw 48-terminal tqfp package product highlights 1. on-chip input clamp and cds clamp circuitry and high speed correlated double sampler allow for simple ac-coupling to interface a ccd sensor at full 18 msps conversion rate. 2. on-chip pga the AD9802 includes a low-noise, wideband amplifier with analog variable gain from 0 db to 31.5 db (linear in db). 3. direct adc input a direct input to the 10-bit a/d converter is provided for digitizing video signals. 4. 10-bit, high speed a/d converter a linear 10-bit adc is capable of digitizing ccd signals at the full 18 msps conversion rate. typical dnl is 0.5 lsb and no missing code performance is guaranteed. 5. low power at 185 mw, and 15 mw in power-down, the AD9802 con- sumes a fraction of the power of presently available multichip solutions. 6. digital i/o functionality the AD9802 offers three-state digital output control. 7. small package packaged in a 48-terminal, surface-mount thin quad flatpack, the AD9802 is well suited to very compact, low headroom designs. product description the AD9802 is a complete ccd signal processor developed for electronic cameras. it is suitable for both camcorder and consumer -level still camera applications. the signal processing chain is comprised of a high speed cds, variable gain pga and 10-bit adc. required clamping cir- cuitry and an onboard voltage reference are provided as well as a direct adc input. the AD9802 operates from a single +3 v supply with a typical power consumption of 185 mw. the AD9802 is packaged in a space saving 48-terminal thin quad flatpack (tqfp) and is specified over an operating tem- perature range of 0 c to +70 c.
C2C rev. 0 AD9802Cspecifications (t min to t max with acvdd = 3.15 v, advdd = 3.15 v, dvdd = 3.15 v, drvdd = 3.15 v unless otherwise noted) parameter min typ max units temperature range operating 0 70 c storage C65 150 c power supply voltage (for functional operation) acvdd 3.00 3.15 3.50 v advdd 3.00 3.15 3.50 v dvdd 3.00 3.15 3.50 v drvdd 3.00 3.15 3.50 v power supply current acvdd 39.5 ma advdd 14.6 ma dvdd 4.7 ma drvdd 0.07 ma power consumption normal operation 185 mw power-down mode 15 mw maximum shp, shd, adcclk rate 18 mhz adc resolution 10 bits differential nonlinearity 0.5 lsbs no missing codes guaranteed adcclk rate 18 mhz reference top voltage 1.75 v reference bottom voltage 1.25 v input range 1.0 v p-p cds maximum input signal 500 mv p-p pixel rate 18 mhz pga 1 maximum gain 31.5 db high gain 14.5 19 23.5 db medium gain 1.0 4.0 7.0 db minimum gain C4.0 0 +4 db clamp (during clpob. only stable over pga range 0.3 v to 2.7 v) average black level 32 lsbs pixel-to-pixel offset (see black level clamping for description) 2 8 lsbs notes 1 pga test conditions: maximum gain pgacont1 = 2.7 v, pgacont2 = 1.5 v; high gain pgacont1 = 2.0 v, pgacont2 = 1.5 v; medium gain pgacont1 = 0.5 v, pgacont2 = 1.5 v; minimum gain pgacont1 = 0.3 v, pgacont2 = 1.5 v. specifications subject to change without notice. digital specifications parameter symbol min typ max units logic inputs high level input voltage v ih 2.4 v low level input voltage v il 0.6 v high level input current i ih 10 m a low level input current i il 10 m a input capacitance c in 10 pf logic outputs high level output voltage v oh 2.4 v low level output voltage v ol 0.6 v i oh 50 m a i ol 50 m a (t min to t max with acvdd = 3.15 v, advdd = 3.15 v, dvdd = 3.15 v, drvdd = 3.15 v unless otherwise noted)
AD9802 C3C rev. 0 timing specifications parameter min typ max units adcclk clock period 55.6 ns adcclk hi-level period 24.8 27.8 ns adcclk lo-level period 24.8 27.8 ns shp, shd clock period 55.6 ns shp, shd minimum pulse width 12.5 ns shp rising edge to shd rising edge 28 ns digital output delay 20 ns digital output data control pblk mode1 mode2 digital output data (d9Cd0) 0 0 0 0000000000 1 0 0 normal operation 1 0 1 1010101010 1 1 0 0101010101 1 1 1 high impedance (t min to t max with acvdd = 3.15 v, advdd = 3.15 v, dvdd = 3.15 v, drvdd = 3.15 v unless otherwise noted) absolute maximum ratings* parameter with respect to min max units advdd advss, subst C0.3 6.5 v acvdd acvss, subst C0.3 6.5 v dvdd dvss, dsubt C0.3 6.5 v drvdd drvss, dsubst C0.3 6.5 v shp, shd dsubst C0.3 dvdd + 2.0 v adcclk, clpob, clpdm dsubst C0.3 dvdd + 0.3 v pgacont1, pgacont2 subst C0.3 acvdd + 0.3 v pin, din subst C0.3 acvdd + 0.3 v dout dsubst C0.3 drvdd + 0.3 v vrt, vrb subst C0.3 advdd + 0.3 v clamp_bias subst C0.3 acvdd + 0.3 v ccdbyp1, ccdbyp2 subst C0.3 acvdd + 0.3 v stby dsubst C0.3 dvdd + 0.3 v mode1, mode2 subst C0.3 advdd + 0.3 v drvss, dvss, acvss, advss subst, dsubst C0.3 +0.3 v junction temperature +150 c storage temperature C65 +150 c lead temperature (10 sec) +300 c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating o nly; functional operation of the device at these or other conditions above those indicated in the operational sections of this specification is not implied. exposure t o absolute maximum ratings for extended periods may affect device reliability. ordering guide model temperature range package description package option AD9802jst 0 c to +70 c 48-terminal plastic thin quad flatpack st-48 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD9802 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
AD9802 C4C rev. 0 pin function descriptions pin # pin name type description 1 advss p analog ground 2C11 d0Cd9 do digital data outputs: d0 = lsb, d9 = msb 12 drvdd p +3 v digital driver supply 13 drvss p digital driver ground 14 dsubst p digital substrate 15 dvss p digital ground 16 adcclk di adc sample clock input 17 dvdd p +3 v digital supply 18 stby di power-down (active high) 19 pblk di pixel blanking (active low) 20 clpob di black level restore clamp (active low) 21 shp di reference sample clock input 22 shd di data sample clock input 23 clpdm di input clamp (active low) 24 dvss p digital ground 25 ccdbyp2 ao ccd bypass. decouple to analog ground through 0.1 m f. 26 din ai cds input. tie to pin 27 and ac-couple to ccd output through 0.1 m f. 27 pin ai cds input. see above. 28 ccdbyp1 ao ccd bypass. decouple to analog ground through 0.1 m f. 29 pgacont1 ai coarse pga gain control (0.3 vC2.7 v). decoupled to analog ground through 0.1 m f. 30 pgacont2 ai fine pga gain control 31 acvss p analog ground 32 clamp_bias ao clamp bias level. decouple to analog ground through 0.1 m f. 33 acvdd p +3 v analog supply 34, 35 test1, test2 ai reserved test pins. should be left nc or pulled high to acvdd. 36 adcin ai direct adc analog input (see driving the direct adc input) 37 cmlevel ao common-mode level. decouple to analog ground through 0.1 m f. 38 shabyp ao internal bias level. decouple to analog ground through 0.1 m f. 39 mode2 di adc test mode control (see digital output data control.) 40 mode1 di adc test mode control (see digital output data control.) 41 adcmode di adc input control. logic low for cds/pga, high for direct input. 42 nc no connect 43 advdd p +3 v analog supply 44, 45 advss p analog ground 46 subst p substrate. connect to analog ground. 47 vrb ao bottom reference bypass. decouple to analog ground through 0.1 m f. 48 vrt ao top reference bypass note type: ai = analog input, ao = analog output, di = digital input, do = digital output, p = power. pin configuration 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) dvdd dsubst dvss adcclk stby advss (lsb) d0 d1 d2 d3 d4 d5 d6 d7 d8 (msb) d9 drvdd nc = no connect pblk clpob shp shd AD9802 dvss adcin test2 test1 acvdd clamp_bias acvss pgacont2 pgacont1 ccdbyp1 pin din ccdbyp2 vrt vrb subst advss advss advdd nc adcmode mode1 mode2 shabyp cmlevel clpdm drvss
AD9802 C5C rev. 0 equivalent input circuits dvdd drvdd dvss drvss figure 1. pins 2C11 (db0Cdb9) dvdd dsubst dvss 200 v figure 2. pin 21 (shp) and pin 22 (shd) dvdd dsubst dvss 200 v figure 3. pin 16 (adcclk) advdd advss 9.3k v figure 4. pin 37 (cmlevel) acvdd subst acvss 50 v figure 5. pin 25 (ccdbyp2) and pin 28 (ccdbyp1) acvdd subst acvss 50 v 10pf figure 6. pin 26 (din) and pin 27 (pin) acvdd subst acvdd 1k v 8k v 8k v 10k v pgacont1 pgacont2 figure 7. pin 29 (pgacont1) and pin 30 (pgacont2) acvdd subst acvss 10k v 30k v 200 v figure 8. pin 32 (clamp bias) advdd subst advss 3k v 200 v 1.1k v figure 9. pin 48 (vrt) and pin 47 (vrb) acvdd subst 1pf 50 v figure 10. pin 36 (adcin) and pin 38 (shabyp)
AD9802 C6C rev. 0 effective pixel interval black level interval blanking interval dummy black interval effective pixel interval ccd shp shd clpob pblk clpdm adcclk adc data notes: clpdm and clpob overwrite pblk clamp timing needs to be adjusted relative to ccd's black pixels recommended pulse width clpdm = 1.5
AD9802 C7C rev. 0 ccd signal (delayed to match actual sampling edge) shd t id 35ns 35ns t od t h data n? data n n+1 n+2 n+3 n n+4 1234567 shp actual sampling edge adcclk digital out output load c l = 20pf output delay t od = 15ns latency = 5 cycles internal clock delay t id = 3ns hold time t h = 2ns figure 12. timing diagram shp 20ns shd adcclk 5ns 10ns 5ns rising edge anywhere in this period ok inhibited period for adcclk rising edge pre-adc output latch pre-adc output latch data transition figure 13. adcclk timing edge
AD9802 C8C rev. 0 theory of operation introduction the AD9802 is a 10-bit analog-to-digital interface for ccd cameras. the block level diagram of the system is shown in figure 14. the device includes a correlated double sampler (cds), 0 dbC31 db variable gain amplifier (pga), black level correction loop, input clamp and voltage reference. the only external analog circuitry required at the system level is an emit- ter follower buffer between the ccd output and AD9802 inputs. clamp cds black level pga 10-bit adc ref out gain in figure 14. correlated double sampling (cds) cds is important in high performance ccd systems as a method for removing several types of noise. basically, two samples of the ccd output are taken: one with the signal present (data) and one without (reference). subtracting these two samples re moves any noise that is common toor correlates withboth. figure 15 shows the block diagram of the AD9802s cds. the s/h blocks are directly driven by the input and the sampling function is performed passively, without the use of amplifiers. this implementation relies on the off-chip emitter follower buffer to drive the two 10 pf sampling capacitors. only one capacitor at a time is seen at the input pin. the AD9802 actually uses two cds circuits in a ping-pong fashion to allow the system more acquisition time. in this way, the output from one of the two cds blocks will be valid for an entire clock cycle. thus, the bandwidth requirement of the subsequent gain stage is reduced as compared to that for a single cds channel system. this lower bandwidth translates to lower power and noise. 10pf q1 s/h q2 s/h s out from ccd figure 15. programmable gain amplifier (pga) the on-chip pga provides a (linear in db) gain range of 0 dbC 31.5 db. a typical gain characteristic plot is shown in figure 16. only the range from 0.3 v to 2.7 v is intended for actual use. gain ?db pgacont1 ?volts 35 ?5 03 0.5 1 1.5 2 2.5 30 15 0 ? ?0 25 20 10 5 figure 16. as shown in figure 17, pga control is provided through the pgacont1 and pgacont2 inputs. pgacont1 provides coarse, and pgacont2 fine (1/16), gain control.
AD9802 C9C rev. 0 the actual implementation of this loop is slightly more compli- cated as shown in figure 19. because there are two separate cds blocks, two black level feedback loops are required and two offset voltages are developed. figure 19 also shows an addi- tional pga block in the feedback loop labeled rpga. the rpga uses the same control inputs as the pga, but has the inverse gain. the rpga functions to attenuate by the same factor as the pga amplifies, keeping the gain and bandwidth of the loop constant. there exists an unavoidable mismatch in the two offset voltages used to correct both cds blocks. this mismatch causes a slight difference in the offset level for odd and even pixels, called pixel-to-pixel offset (see specifications). the pixel-to-pixel offset is an output referred specification, because the black level correction is done using the output of the pga. pga adc in clpob neg ref control cds1 rpga2 int2 cds2 rpga1 int1 figure 19. input bias level clamping the buffered ccd output is connected to the AD9802 through an external coupling capacitor. the dc bias point for this cou- pling capacitor is established during the clamping (clpdm = low) period using the dummy clamp loop shown in figure 20. when closed around the cds, this loop establishes the desired dc bias point on the coupling capacitor. black level clp ccd input clamp clpdm to adc pga cds figure 20. input blanking in some applications, the AD9802s input may be exposed to large signals from the ccd. these signals can be very large, relative to the AD9802s input range, and could thus saturate on-chip circuit blocks. recovery time from such saturation conditions could be substantial. to avoid problems associated with processing these transients, the AD9802 includes an input blanking function. when active (pblk = low) this function stops the cds operation and allows the user to disconnect the cds inputs from the ccd buffer. if the input voltage exceeds the supply rail by more than 0.3 v, then protection diodes will be turned on, increasing current flow into the AD9802 (see equivalent input circuits). such voltage levels should be externally clamped to prevent device damage or reliability degradation. 10-bit analog-to-digital converter (adc) the adc employs a multibit pipelined architecture that is well suited for high throughput rates while being both area and power efficient. the multistep pipeline presents a low input capacitance resulting in lower on-chip drive requirements. a fully differential implementation was used to overcome head- room constraints of the single +3 v power supply. direct adc input the analog processing circuitry may be bypassed in the AD9802. when adcmode (pin 41) is taken high, the adcin pin provides a direct input to the sha. this feature allows digitization of signals that do not require cds and gain adjustment. the pga output is disconnected from the sha when adcmode is taken high. differential reference the AD9802 includes a 0.5 v reference based on a differential, continuous-time bandgap cell. use of an external bypass capaci- tor reduces the reference drive requirements, thus lowering the power dissipation. the differential architecture was chosen for its ability to reject supply and substrate noise. recommended decoupling shown in figure 21. vrt ref vrb 1 m f 0.1 m f 0.1 m f figure 21. internal timing the AD9802s on-chip timing circuitry generates all clocks necessary for operation of the cds and adc blocks. the user needs only to synchronize the shp and shd clocks with the ccd waveform, as all other timing is handled internally. the adcclk signal is used to strobe the output data, and can be adjusted to accommodate desired timing.
AD9802 C10C rev. 0 applications information generating clock signals for best performance, the AD9802 should be driven by 3 v logic levels. as shown in the equivalent input circuits, the use of 5 v logic for adcclk will turn on the protection diode to dvdd, increasing the current flow into this pin. as a result, noise and power dissipation will increase. the cds clock in- puts, shp and shd, have a additional protection and can with- stand direct 5 v levels. external clamping diodes or resistor dividers can be used to translate 5 v levels to 3 v levels, but the lowest power dissi- pation is achieved with a logic transceiver chip. national semiconductors 74lvx4245 provides a 5 v to 3 v level shift for up to eight clock signals, has a three-state option, and features low power consumption. philips semiconductor and quality also manufacture similar devices. driving the direct adc input the AD9802 can be used in a direct adc input mode, in which the input signal bypasses the input clamp, cds and pga, and is sent directly to the sample and hold amplifier (sha) of the adc. there are several methods that may be used to drive the direct adc input. to enable the direct input mode of operation, adcmode (pin 41) is taken to logic high. this will internally disconnect the pga output from the sha input, and connect adcin (pin 36) to the sha input. the sha has a differential input, consisting of adcin (pin 36) as the positive input, and shabyp (pin 38) as the negative input. both pins must be properly dc biased. figures 22 through 25 show four circuits for driving the direct adc input. decoupling capacitors are not shown for cml, vrt, vrb and shabyp pins. sha adcin cml shabyp 1.5v 1v p-p cml +3v adcmode AD9802 figure 22. dc-coupled input figure 22 is a single-ended, dc-coupled circuit. shabyp is connected to cml (1.5 v) to establish a midpoint bias. the input signal of 1 v p-p should be centered around cml. figure 23 shows an ac-coupled configuration, where both inputs are biased to cml. the input capacitor c in and bias resistors should be sized to set the appropriate high pass cutoff frequency for the application. to minimize the differential offset voltage due to the input bias currents, both resistors should be equal. sha adcin cml shabyp 1.5v 1v p-p +3v adcmode AD9802 r bias r bias c in figure 23. ac-coupled input figure 24 shows an alternative ac-coupled configuration. by connecting shabyp to cml, the dc bias at pin 36 (adcin) will internally track to the same voltage, automatically setting the input bias level. with a given input capacitor value, c in , the time constant in this configuration will be dependent on the sampling frequency f s . specifically: t = ( c in / f s ) 2 e +12 sha adcin cml shabyp 1.5v 1v p-p +3v adcmode AD9802 c in figure 24. auto bias ac-coupled input figure 25 shows a true differential drive circuit. each input would be 500 mv p-p, to achieve the 1 v full-scale input to the adc. the common-mode input range for this configuration extends from about 500 mv to 2.5 v. this circuit could also be implemented with ac coupling, similar to figure 23. sha adcin cml shabyp 500mv p-p +3v adcmode AD9802 500mv p-p figure 25. differential input figure 26 shows a video clamp circuit which may be used with the direct adc mode of the AD9802 (supplies and decoupling not shown). the circuit will clamp the reference black level of an incoming video signal to 1.25 v dc. with shabyp con- nected to 1.75 v (vrt), the adcin range spans from 1.25 v to 2.25 v. to accomplish this, the clamp pulse should be asserted during the horizontal sync interval, when the video is at its reference black level. a 5 v logic high applied to the gate of the sd210 will turn on the device, and the input capacitor c in will charge up to provide 1.25 v at the adcin pin of the AD9802. other appropriate nmos devices may be substituted for the sd210. the ad8047 op amp requires 5 v supplies; appropriate single supply op amps may be substituted. the size of capacitor c in should be set to meet the acquisition time and
AD9802 C11C rev. 0 droop specifications needed. a capacitor value of 0.01 m f will result in a droop of less than 10 lsb across one video line, and requires only a clamp pulse of 1 m s to charge up. a larger capacitor may be used to reduce droop, but then a longer clamp pulse may be necessary. sha adcin cml shabyp 1v p-p +3v adcmode AD9802 vrt 500 v c in clamp ad8047 500 v sd210 vrb figure 26. video clamp circuit 1.0 0 2 1.0 0 600 100 200 300 400 500 0.5 2 0.5 700 800 900 1023 figure 27. direct adc-mode typical inl 1.0 0 2 1.0 0 600 100 200 300 400 500 0.5 2 0.5 700 800 900 1023 figure 28. direct adc-mode typical dnl frequency C mhz 0 C100 0 9.0 amplitude C db figure 29. direct adc mode typical fft; f in = 3.58 mhz, f s = 18 mhz figures 27C29 show the typical linearity and distortion perfor- mance of the AD9802 in direct adc mode. digitally programmable gain control the AD9802s pga is controlled by an analog input voltage of 0.3 v to 2.7 v. in some applications, digital gain control is preferable. figure 30 shows a circuit using analog devices ad8402 digital potentiometer to generate the pga control voltage. the ad8402 functions as two individual potentiom- eters, with a serial digital interface to program the position of each wiper over 256 positions. the device will operate with 3 v or 5 v supplies, and features a power-down mode and a reset function. to keep external components to a minimum, the ends of the potentiometers can be tied to ground and +3 v. one pot is used for the coarse gain adjust, pgacont1, with steps of about 0.2 db/lsb. the other pot is used for fine gain control, pgacont2, and is capable of around 0.01 db steps if all eight bits are used. the two outputs should be filtered with 1 m f or larger capacitors to minimize noise into the pgacont pins of the AD9802. 14 13 12 11 10 9 8 1 2 3 4 5 6 7 ad8402-10 +3v +3v sdi clk rs shdn cs 0.1 m f1 m f +3v pgacont1 1 m f pgacont2 figure 30. digital control of pga
AD9802 C12C rev. 0 the disadvantage of this circuit is that the control voltage will be supply dependent. if additional precision is required, an external op amp can be used to amplify the vreft (1.75 v) or vrefb (1.25 v) pins on the AD9802 to the desired voltage level. these reference voltages are stable over the operating supply range of the AD9802. low power, low cost, rail-to-rail output amplifiers like the ad820, op150 and op196 are speci- fied for 3 v operation. alternatively, a precision voltage refer- ence may be used. the ref193 from analog devices features low power, low dropout performance, maintaining a 3 v output with a minimum 3.1 v supply when lightly loaded. power and grounding recommendations the AD9802 should be treated as an analog component when used in a system. the same power supply and ground plane should be used for all of the pins. in a two-ground system, this requires that the digital supply pins be decoupled to the analog ground plane and the digital ground pins be connected to ana- log ground for best noise performance. if any pins on the AD9802 are connected to the system digital ground, then noise can capacitively couple inside the AD9802 (through package and die parasitics) from the digital circuitry to the analog circuitry. separate digital supplies can be used, particularly if slightly different driver supplies are needed, but the digital power pins should still be decoupled to the same point as the digital ground pins (analog ground plane). if the AD9802 digi- tal outputs need to drive a bus or substantial load, a buffer should be used at the AD9802s outputs, with the buffer refer- enced to system digital ground. in some cases, when system digital noise is not substantial, it is acceptable to split the ground pins on the AD9802 to separate analog and digital ground planes. if this is done, be sure to connect the ground pins together at the AD9802. to further improve performance, isolating the driver supply drvdd from dvdd with a ferrite bead can help reduce kick- back effects during major code transitions. alternatively, the use of damping resistors on the digital outputs will reduce the out- put rise times, reducing the kickback effect. evaluation board an evaluation board for the AD9802 is available. the board includes circuitry for manual pga gain adjustment, input signal buffering, and logic level translation for 3 v or 5 v digital signals. documentation for the AD9802-eb is included, consisting of a board description, schematic and layout information. ad9801/AD9802 evaluation board description power supply connectors j1 vdd: +3 v supply for the ad9801/AD9802. data sheet specifications are given for +3.15 v. operational range is from +3 v to +3.5 v. j2 avcc: +5 v supply for the ad8047 buffer, and for the pgacont and pin potentiometers. if the buffer am- plifier is not needed, avcc may be connected to the vdd supply. j3 avss: C5 v supply for the ad8047 buffer. if the buffer amplifier is not needed, avss may be connected to j4. j4 agnd: this is the analog ground plane for the ad9801/AD9802 and the buffer amplifier. the two ground planes are already connected together in one place on the evaluation board. j5 dgnd: this is the digital ground plane for the lvxc3245 transceivers. the two ground planes are already connected together in one place on the evalua- tion board. j6 +3d: +3 v digital supply for the lvxc3245 transceivers. j7 +3/5d: +3 v or +5 v digital supply for the lvxc3245 transceivers. this voltage determines the logic compat- ibility of the evaluation board. if 3 v clock levels and 3 v digital output levels are to be used, connect +3 v to j7. if +5 v clock levels and +5 digital output levels are to be used, connect +5 v to j7. input connectors j8 din: unbuffered input to the ad9801/AD9802. this input is 50 w terminated by r4, which may be removed if no termination is required. see input configurations for more information. j9 vin: input to the ad8047 buffer amplifier. this input is 50 w terminated by r5, which may be re- moved if no termination is required. this op amp can be used as a buffer to drive the din pin on the ad9801/AD9802, or as a buffer for driving the direct adc input on the AD9802. see input configurations and the AD9802 data sheet for more information. clock connectors j10 clpdm j11 shd j12 shp j13 clpob j14 pblk j15 adcclk all of the clock inputs are 50 w terminated and buffered by an lvxc3245 transceiver. the supply level at j7 determines the input clock level compatibility. the outputs of the lvxc3245 always send +3 v clock levels to the ad9801/AD9802.
AD9802 C13C rev. 0 input configurations input jp1 jp2 jp3 jp4 jp5 jp8 jp9 jp10 standard ccd input j8 open short open open open open short open grounded input test none open short open short open open short open buffered input* j9 open short open open short open short open direct adc input j9 [ ... dont care... ] short open short (9802 only) *when using the buffer amplifier, 5 v must be connected to avcc and avss, and r4 should be removed. jumper descriptions jp1 connect to bypass the input coupling capacitor c18. jp2 connect to short pin and din (pins 26 and 27 of the ad9801) together. jp3 connects pin to the dc level set by the wiper of r1. jp4 connect to short the input coupling capacitor to ground, for test purposes. jp5 connects the output of the buffer amplifier to the ad9801/AD9802 input. jp6 connects the ad9801/AD9802s drvdd pin to the vdd supply through ferrite bead fb6. jp7 connects the ad9801/AD9802s drvdd pin to the +3d supply. jp8 connects the output of the ad8047 op amp to the direct adc input of the AD9802. this jumper should never be connected on the ad9801-eb. jp9 selects the regular camera mode of operation on the AD9802 . this jumper should always be in place on the ad9801-eb. jp10 selects the direct adc input mode on the AD9802 . this jumper should never be connected on the ad9801-eb. test point descriptions tp1 input signal at j8. tp2 input signal at pin/din of ad9801/AD9802. tp3 pgacont1 voltage. tp4 pgacont2 voltage. tp5 standby pin, pull high to enable power-down mode. tp6 clpdm at ad9801/AD9802. tp7 shd at ad9801/AD9802. tp8 shp at ad9801/AD9802. tp9 clpob at ad9801/AD9802. tp10 pblk at ad9801/AD9802. tp11 adcclk at ad9801/AD9802. tp12 vdd tp13 avcc tp14 avss tp15 agnd tp16 dgnd tp17 +3d tp18 +3/5d prototype area the top left hole in the prototyping area is connected to agnd. the bottom right hole is connected to avcc.
AD9802 C14C rev. 0 c5 0.1 m f c6 0.1 m f jp9 c3 0.1 m f c2 0.1 m f c1 1 m f c4 0.1 m f c55 0.01 m f vdd jp10 r1 1k v c13 0.1 m f c16 0.1 m f c17 0.01 m f jp7 jp6 fb6 adcclk pblk clpob shp shd clpdm d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 c56 0.1 m f c18 0.1 m f pgacont1 pgacont2 jp2 jp1 c19 0.1 m f tp1 tp2 jp3 cw avcc jp4 r4 50 v din j8 jp8 amp_out +3d vdd vdd vdd c14 0.1 m f c15 0.01 m f tp5 tp10 tp9 tp8 tp7 tp6 tp11 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 39 38 37 43 42 41 40 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 drvss dsubst dvss adcclk dvdd stby pblk clpob shp shd clpdm dvss adcin test2 test1 acvdd acvss pgacont2 pgacont1 ccdbyp1 pin din ccdbyp2 clamp_bias advss d0 (lsb) d1 d2 d3 d4 d5 d6 d7 d8 d9 (msb) drvdd vrt vrb subst advss advss advdd advdd adcmode mode1 mode2 shabyp cmlevel c8 0.1 m f c9 0.1 m f jp5 c10 0.1 m f c11 0.1 m f c12 0.1 m f u1 AD9802 figure 31. evaluation board
AD9802 C15C rev. 0 pgacont1 tp3 cw avcc c31 0.1 m f r2 10k v c30 10 m f 16v j1 fb1 tp12 vdd +3v c36 0.1 m f c35 22 m f c34 0.1 m f j7 fb5 tp18 +3/5d +3/5d c48 0.1 m f c47 22 m f c46 0.1 m f j5 tp16 dgnd j2 fb2 tp13 avcc +5v c39 0.1 m f c38 22 m f c37 0.1 m f j3 fb3 tp14 avss C5v c42 0.1 m f c41 22 m f c40 0.1 m f j4 tp15 gnd j6 fb4 tp17 +3d +3d c45 0.1 m f c44 22 m f c43 0.1 m f pgacont2 tp4 cw avcc c33 0.1 m f r3 10k v c32 10 m f 16v vin avss j9 amp_out avcc c21 0.01 m f c20 1.0 m f r5 50 v r6 20 v u2 ad8047 r13 500 v c23 0.01 m f c22 1.0 m f figure 32. evaluation board
AD9802 C16C rev. 0 2 10 20 30 40 1 3 5 7 9 11 13 15 17 19 21 23 33 40-pin header db9 (msb) db8 db7 db6 db5 db4 db3 db2 db1 db0 (lsb) clkout j16 1 2 3 4 5 6 7 8 9 10 11 12 74lvxc3245 c53 0.1 m f +3d d9 d8 d7 d6 d5 d4 d3 d2 v cc a t/r b a0 a2 a4 a6 a5 a3 a1 gnd gnd a6 v cc b nc oe b b0 b1 b2 b3 b4 b5 b6 b7 gnd u4 db9 db8 db7 db6 db5 db4 db3 db2 24 23 22 21 19 17 15 20 18 16 14 13 c26 0.01 m f c27 0.01 m f c50 0.1 m f +3/5d 1 2 3 4 5 6 7 8 9 10 11 12 74lvxc3245 c54 0.1 m f +3d clpdm shd shp clpob pblk adcclk v cc a t/r b a0 a2 a4 a6 a5 a3 a1 gnd gnd a6 v cc b nc oe b b0 b1 b2 b3 b4 b5 b6 b7 gnd u3 24 23 22 21 19 17 15 20 18 16 14 13 c24 0.01 m f c25 0.01 m f c49 0.1 m f +3/5d r9 50 v shp j12 r10 50 v clpob j13 r7 50 v clpdm j10 r8 50 v shd j11 r11 50 v pblk j14 r12 50 v adcclk j15 1 2 3 4 5 6 7 8 9 10 11 12 74lvxc3245 c52 0.1 m f +3d d1 d0 adcclk v cc a t/r b a0 a2 a4 a6 a5 a3 a1 gnd gnd a6 v cc b nc oe b b0 b1 b2 b3 b4 b5 b6 b7 gnd u5 db1 db0 clkout 24 23 22 21 19 17 15 20 18 16 14 13 c28 0.01 m f c29 0.01 m f c51 0.1 m f +3/5d figure 33. evaluation board
AD9802 C17C rev. 0 figure 34. primary side (layer 1) figure 35. ground plane (layer 2)
AD9802 C18C rev. 0 figure 36. power plane (layer 3) figure 37. secondary layer (layer 4)
AD9802 C19C rev. 0 figure 38. primary side assembly figure 39. secondary side assembly
C20C c3102C3C10/97 printed in u.s.a. AD9802 rev. 0 outline dimensions dimensions shown in inches and (mm). 48-terminal plastic thin quad flatpack (tqfp) (st-48) 0.354 (9.00) bsc 0.276 (7.0) bsc 1 12 13 25 24 36 37 48 top view (pins down) 0.276 (7.0) bsc 0.354 (9.00) bsc 0.011 (0.27) 0.006 (0.17) 0.019 (0.5) bsc seating plane 0.063 (1.60) max 0 min 0 ?7 0.076 max 0.030 (0.75) 0.018 (0.45) 0.057 (1.45) 0.053 (1.35) 0.030 (0.75) 0.018 (0.45) 0.007 (0.18) 0.004 (0.09)

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